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Sheet目录3753

96页 97页 98页 99页 [100页]101页 102页 103页 104页

2005 Microchip Technology Inc.

Preliminary

DS41265A-page 187

PIC16F946

FIGURE 15-5:

SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 15-6) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 15-6:

PWM OUTPUT

15.3.1

PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

TMR2 is cleared

The RC5/T1CKI/CCP1/SEG10 pin is set

(exception: if PWM duty cycle = 0%, the

RC5/T1CKI/CCP1/SEG10 pin will not be set)

The PWM duty cycle is latched from CCPR1L into

CCPR1H

15.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitch-free PWM operation.

When the CCPR1H and 2-bit latch match TMR2, con-

catenated with an internal 2-bit Q clock, or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the formula:

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<5>

RC5/T1CKI/

Note

The 8-bit timer is concatenated with 2-bit internal Q

clock, or 2 bits of the prescaler, to create 10-bit time

base.

CCP1/SEG10

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

PWM period = (PR2) + 1] 4 TOSC

(TMR2 prescale value)

Note:

The Timer2 postscaler (see Section 7.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Note:

If the PWM duty cycle value is longer than

the

PWM

period,

the

RC5/T1CKI/CCP1/SEG10 pin will not be

cleared.

PWM duty cycle =(CCPR1L:CCP1CON<5:4>)

TOSC (TMR2 prescale value)

PWM Resolution

FOSC

FPWM

TMR2 Prescaler

-------------------------------------------------------------

log

()

log

---------------------------------------------------------------------------bits

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